During the last ten years or so, I've interfaced with literally thousands of students, usually in their last year of engineering or Master's degree program in some college and other, usually in electronics or instrumentation.
What I found surprising was that more than 80% of these students simply had no concrete idea about what Tri-State is about. I think, that I have a reasonable idea about what tri-state is, and I'll get some of my thoughts across.
To begin with let us talk about digital logic. By definition digital logic devices (gates,flip flops etc.) will give only one of the two voltage levels as output. A Logic Zero (Usually within few millivolts of the GND reference terminal, dependent upon how much current is being sunk into the output), and a Logic One (Usually within few millivolts of the VDD reference terminal, dependent upon how much current is being pulled from it).
A typical logic output structure (TTL) looks like the figure 1. TTL stands for Transistor-Transistor Logic and usually is run from a 5V (+/- 5%) supply voltage. This figure of course does not depi
ct a full TTL stage but is good enough for our discussion.
When the output is Logic One, the upper transistor is On, presenting a low resistance path to +5V, and when output is Logic Zero, the lower transistor is On, presenting a low resistance to GND. The logic block driving the transistors makes sure that both transistors NEVER turn on simultaneously. If they were to turn on together the +5V supply would effectively be shorted to ground through a small resistance, and the resulting current would destroy the output stage.
Figure 1
Now, if an additional transistor were added, like in the Figure 2, and if both inputs to the output stage were
pulled low by turning on the extra transistor added at the bottom, then both the output stage transistors will be in the OFF state, irrespective of the inputs presented to the logic block.
Since both transistors are in the OFF state, they would end up presenting a very large resistance (impedance!) to both ground as well as the supply rail. Under this circumstance, if an external voltage (0 < Vext < Vsupply) were inserted on the Vout pin, it would not matter.
Under this condition the output of our logic device is in a high impedance state. This is called tri-state.
A practical application of tri-state is that it allows many logic gate outputs to be connected to the same bus, and then by enabling only one gate at a time, keeping other outputs in tri-state, it is possible to poll many outputs. Read up on 74LS125 to get an idea. The same technique is used to tri-state data bus outputs in many parallel interface chips (e.g. the 74xx245 bus driver or 64256 like SRAM chips, LCDs etc.)
A quick way to check tri-state is to measure the voltage at output of a logic gate with a simple DMM. The high impedance of the transistors will effectively form a voltage divider (loaded to a small extent by the DMM's input impedance) and would end up showing a voltage approximately half of supply voltage.
This test can fail sometimes, if there are leakage paths available on the board. The leakage paths will end up providing enough current to either pull-up or pull-down the output of the gate. Under these circumstances, simply touch the DMM probe (the one that is put on the Vout node) with your finger. If the voltage changes then the output is almost guaranteed to be in tri-state.
This trick will NOT work very well if there are low value (< 10k) pull up resistors connected on the pins, or if there are other devices connected to the same output that might drive the output to some specific voltage.
If you find any obvious mistakes in what I have written here please do get back and bite, so I can correct those mistakes.
What I found surprising was that more than 80% of these students simply had no concrete idea about what Tri-State is about. I think, that I have a reasonable idea about what tri-state is, and I'll get some of my thoughts across.
To begin with let us talk about digital logic. By definition digital logic devices (gates,flip flops etc.) will give only one of the two voltage levels as output. A Logic Zero (Usually within few millivolts of the GND reference terminal, dependent upon how much current is being sunk into the output), and a Logic One (Usually within few millivolts of the VDD reference terminal, dependent upon how much current is being pulled from it).
A typical logic output structure (TTL) looks like the figure 1. TTL stands for Transistor-Transistor Logic and usually is run from a 5V (+/- 5%) supply voltage. This figure of course does not depi
ct a full TTL stage but is good enough for our discussion.When the output is Logic One, the upper transistor is On, presenting a low resistance path to +5V, and when output is Logic Zero, the lower transistor is On, presenting a low resistance to GND. The logic block driving the transistors makes sure that both transistors NEVER turn on simultaneously. If they were to turn on together the +5V supply would effectively be shorted to ground through a small resistance, and the resulting current would destroy the output stage.
Figure 1
Now, if an additional transistor were added, like in the Figure 2, and if both inputs to the output stage were
pulled low by turning on the extra transistor added at the bottom, then both the output stage transistors will be in the OFF state, irrespective of the inputs presented to the logic block.
Since both transistors are in the OFF state, they would end up presenting a very large resistance (impedance!) to both ground as well as the supply rail. Under this circumstance, if an external voltage (0 < Vext < Vsupply) were inserted on the Vout pin, it would not matter.
Under this condition the output of our logic device is in a high impedance state. This is called tri-state.
A practical application of tri-state is that it allows many logic gate outputs to be connected to the same bus, and then by enabling only one gate at a time, keeping other outputs in tri-state, it is possible to poll many outputs. Read up on 74LS125 to get an idea. The same technique is used to tri-state data bus outputs in many parallel interface chips (e.g. the 74xx245 bus driver or 64256 like SRAM chips, LCDs etc.)
A quick way to check tri-state is to measure the voltage at output of a logic gate with a simple DMM. The high impedance of the transistors will effectively form a voltage divider (loaded to a small extent by the DMM's input impedance) and would end up showing a voltage approximately half of supply voltage.
This test can fail sometimes, if there are leakage paths available on the board. The leakage paths will end up providing enough current to either pull-up or pull-down the output of the gate. Under these circumstances, simply touch the DMM probe (the one that is put on the Vout node) with your finger. If the voltage changes then the output is almost guaranteed to be in tri-state.
This trick will NOT work very well if there are low value (< 10k) pull up resistors connected on the pins, or if there are other devices connected to the same output that might drive the output to some specific voltage.
If you find any obvious mistakes in what I have written here please do get back and bite, so I can correct those mistakes.
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